CVC is a truly industrial strength Verilog simulator, something that the EDA world desperately needs. It WILL do FULLY back-annotated SDF simulations for ASIC and FPGA designs, it is compiled and FAST, and is open source.
It is a project that definitely deserves attention.
http://www.prnewswire.com/news-releases/pragmatic-c-software...
Also, any relation to GPL cver?
https://sourceforge.net/projects/gplcver/