I believe this is a relevant source: http://www.arm.com/products/system-ip/inter... | Hacker News

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		ganzuul on Nov 1, 2014 \| parent \| context \| favorite \| on: How L1 and L2 CPU caches work, and why they’re an ... I believe this is a relevant source: http://www.arm.com/products/system-ip/interconnect/corelink-... The L3 cache is 'integrated', which I presume means it's different names for the same thing.

shortsightedsid on Nov 2, 2014 [–]

Ah! Thanks for sharing. It is for ARMv8 which I really need to read up on.

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