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Good point. Any idea what ballpark speed one would need?



Speed of the FPGA? FPGAs are given speed grades, but the actual design dictates the max speed. Different logic sections, depending on pipelining, size, which pins they are connected to can run at different speeds. You might have an overall max speed/critical path of say 50mhz, but you might be able to safely run a small section of the design at 200mhz.


But, you can make your calculations massively parallel on an FPGA. So the clock speed does not compare at all to a typical processor.




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