Your math is a bit off. 128 lanes gen5 is 8 times x16, which has a combined theoretical bandwidth of 512GB/s, and more like 440GB/s in practice after protocol overhead.
Unless we are considering both read and write bandwidth, but that seems strange to compare to memory read bandwidth.
People like to add read and write bandwidth for some silly reason. Your units are off, too, though: gen 5 is 32 GT/s, meaning 64 GB/s (or 512 gigabits per second) each direction on an x16 link.
Unless we are considering both read and write bandwidth, but that seems strange to compare to memory read bandwidth.