You're missing the key point, which is that the size referenced as the semiconductor manufacturing node is no longer an accurate description of the true transistor size, it's more of a marketing term.
Even if it's possible to build transistors that are 1.4nm in size (or smaller), that is not what "1.4nm" means in the context of this announcement. I get that this can be confusing, it's just a case of smoke and mirrors because Moore's Law is already dead and semiconductor manufacturers don't want to spook investors. The performance gains are still real, but the reasons for getting them are no longer as simple as shrinking transistor size.
As for the true physical limits of transistor sizes, there are problems like quantum tunnelling that we aren't likely to overcome, so even if you can build a gate with 7 atoms, that doesn't mean it'll work effectively. Also note that "gate" does not necessarily mean "transistor".
> That's clearly false, have a quick look at this chart
Feels like it's not detailed enough to make an assessment.
For example, if die size is being increased to counter the lack of improvements from transistor shrinking, it may technically meet the criteria set out in Moore's Law, but not in the sense that most people use it as a yard stick for performance improvements.
> if die size is being increased to counter the lack of improvements from transistor shrinking
This definitely doesn't fully explain everything that is happening. Die sizes aren't changing that fast.
Even if it is a part, you're ignoring that it is still a difficult technical challenge. It it weren't we'd see much larger dies. We have a lot of infrastructure around these chips that we're stacking together and the biggest problem in supercomputing and data centers is I/O. People would love to have bigger chips. I mean that's a far better solution than a dual socket mobo.
> This definitely doesn't fully explain everything that is happening. Die sizes aren't changing that fast.
Let's look at a real world comparison.
Based on information I can find online...
* Apple M1 silicon die was 118.91mm2, used TSMC 5nm process node, and had 16 billion transistors.
* Apple M3 silicon die was 168mm2, used TSMC 3nm process node, and had 25 billion transistors.
If you compare these two, you can see that the increased die size did allow for most of the improvements in transistor count. Even if it's not a completely like-for-like comparison, and is not necessarily always as straightforward as this, it's obvious to me that transistor count on it's own is a poor measure of semiconductor process improvements, and a much better measure is transistor density (e.g. comparing how many transistors can fit into a wafer of a fixed size, such as 100mm2).
I'm going to refer you to my other comment, because you did the same thing[0]
Second, let's actually check the math. Just divide the two numbers
- M1 135 million transistors per mm2
- M3 149 million transistors per mm2
So no, the increased die size did not allow for that. If we had the same ratio the M3 would have 22.7 billion transistors. (22.7-16)/(25-16) = 74.4%. I'll give you that this is "most" but 25% is not a rounding error. You gave yourself wiggle room, but that wiggle room is exactly the thing I was talking about and what you're arguing against.
Don't just cherry pick things from what people said and stroke your ego. Sometimes other people aren't completely clueless.
That's a strange way to say you didn't claim that the die size accounted for all of the transistor count improvement.
> Sometimes other people aren't completely clueless.
When did I say they were clueless? At most I've suggested that they're focusing on the wrong thing, that doesn't imply they're totally clueless.
Similarly, you have focused on the wrong thing with the last comment I made. The main point of it was to illustrate that looking at transistor count alone is a poor metric to track manufacturing node progress, and a far better metric is transistor density (i.e. you need to account for both transistor count and die size at the same time, otherwise you can appear to make more progress on transistor count by increasing the die size).
Am I calling you clueless? No. I am suggesting that you need to look at the intention behind what I'm saying.
You already admitted that I only said most, which this qualifies as.
> I literally did the math...
You did, and I'm saying that the transistor per mm2 information is a better metric to track semiconductor manufacturing node improvements than just using transistor counts.
It's really not that hard to understand what I'm saying when you take my comments at face value.
> You're right. But the problem isn't understanding you, it's you understanding others.
The impression I've got from the conversation is that, for the most part, people have agreed with me (after I've clarified my thoughts), but they have disagreed with the way that I've said it (because they're under the impression that I'm seeking to undermine their intelligence). Have I understood what you're referring to?
> they're under the impression that I'm seeking to undermine their intelligence
No, we're under the impression you aren't reading our comments. Or only reading the parts that you want and ignoring the rest, even if it was the main point of the comment in the first place.
Take our conversation. What did I say[0]? I said you can't explain everything by the increasing die size. And added information that scaling is a non-trivial technological challenge than your previous comments suggest.
How do you respond? You ignore the second part, which is actually the most important part. Provide die sizes and transistor accounts to prove your point that it is 'essentially increasing die size'. So I did the math. I agree, 75% is "most" but my comment was, again, about how that 25% is non-trivial. So how do you respond? You again focus on the first part and ignore the second.
I don't feel like you're calling me dumb or undermining my intelligence or something. I feel like I'm talking to someone who only bothers to read half of what I say and questioning myself for why I'm even bothering to respond. So I don't know, I still feel like you're going to reinterpret this as my intelligence being insulted when I really couldn't care less. My real name isn't attached, I really don't care if you think I'm dumb. I'll refer you to my prior comment. You can figure out which one...
> What did I say[0]? I said you can't explain everything by the increasing die size. And added information that scaling is a non-trivial technological challenge than your previous comments suggest.
Scaling is a non-trivial challenge, but that doesn't mean the "Moore's Law" rate of progress is being kept up, or rather it isn't if you treat it as a way to track transistor density. In other words, I don't deny that progress is still being made, but the Moore's Law speed of progress is not.
As for die size not accounting for everything, I've already explained that it doesn't account for everything, but it does account for a large part in perceived technical progress. If you think about it it's quite simple, if the rate of transistor shrinkage has decreased in real physical terms (not in the "5nm", "3nm", etc... marketing terms), there's only a few different ways that can happen and you still end up with chips with a larger number of transistors...
1. You can build out vertically, i.e. stacking multiple transistor layers.
2. You can build out horizontally, i.e. increase the width of the die size.
3. You can try to optimise routing or remove non-transistor components from the chips to free up room.
All three are valid options, but they're not equal in terms of achieving a large boost in transistor count. Option 1 is being worked on and is likely to be more of a feature in upcoming process nodes. Option 3 is useful but limited, in the sense that the routing for these chips is already strongly optimised, and unless you couple it with Option 1 the scope for improvements are limited. This leaves you with Option 2, which is both the easiest and cheapest to achieve with current technology.
With these factors in mind, it's obvious that a large part of how transistor counts keep going up with a slowed rate of improvement in transistor size is going to be through increasing die size.
To help illustrate the point further, take a look at this table of Nvidia GPU die sizes. Note that although the growth is not linear, there is a clear trend towards larger die sizes over time.
Personally I wouldn't argue Moore's law is dead but I do wonder about the cost per chip. WE can still push smaller for a lot longer but the costs are starting to creep up a bit.
I am not too worried though because adjusted for inflation, we are still saying a lot less for this tech than we were in pre-2000's tech.
Economy of scale used to drop prices, complexity of manufacturing will slowly increase them again.
Similar concerns were expressed around the development of VLSI tooling in the '70s. We've been on this curve for a long time. I can speak with some experience that manufacturing of steel and wood products increases similarly in cost and complexity with scale. Beasts like these exist: https://en.wikipedia.org/wiki/Heavy_Press_Program
As long as the scale of production is increasing, additional investments will be warranted.
They also demonstrated knowledge of the very thing you're trying to explain to them. So if you think they are being rude or hostile to you, be aware that, even if unintentionally, you insulted them first. To be honest, even I feel a little offended because I don't know how you read that comment and come away thinking they don't know that 1) the 'x'nm number is not representative, 2) gains are coming from things other than literal physical size, 3) quantum tunneling. They actively demonstrated knowledge of the first two and enough that I suspect they understand the third. I mean it is a complex phenomena that few people understand in depth, but it is also pretty well known and many understand at a very high level.
From a third party perspective: it comes off like you didn't read their comment. I think you're well intentioned, but stepped on a landmine.
What mrb is pointing out is that OP is comparing two different units. The 7 atoms is a count of atoms in a 3d space and is not size dimension. Comparing a count of atoms with physical size of a transistor is problematic.
Even if it's possible to build transistors that are 1.4nm in size (or smaller), that is not what "1.4nm" means in the context of this announcement. I get that this can be confusing, it's just a case of smoke and mirrors because Moore's Law is already dead and semiconductor manufacturers don't want to spook investors. The performance gains are still real, but the reasons for getting them are no longer as simple as shrinking transistor size.
As for the true physical limits of transistor sizes, there are problems like quantum tunnelling that we aren't likely to overcome, so even if you can build a gate with 7 atoms, that doesn't mean it'll work effectively. Also note that "gate" does not necessarily mean "transistor".