There was an ISA I saw a while back that featured an "enhanced multiply and accumulate signed" instruction, which of course got the mnemonic "EMACS"

PowerPC has ‘Enforce In-Order Execution of I/O’ (eieio).

Obscure data point of the day; McDonalds is a small but long-standing real estate company in a provincial city in New Zealand. Their website address? eieio.co.nz

Could it be that they just wanted to call it POWER. And then "Enhanced" RISC made the acronym possible?

At what point have you enhanced your RISC architecture to the point where it becomes CISC?

Unless you're making it possible to access memory on every instruction that takes an argument, or adding more addressing modes that are redundant with ALU operations, or making registers that can only be used for one purpose, etc., it's not really turning into CISC. The acronyms are misnomers, or maybe you just need to think of what's being "reduced" as the number of micro-ops per high-level instruction. Regardless, you don't turn RISC into CISC just by adding more instructions.