DEC had a similar problem when porting VMS from VAX to Alpha - significant chunks of it were written in VAX assembly.
They came up with a rather ingenious solution - a compiler from VAX assembly to Alpha. And that was carried forward into the Itanium and now x86-64 ports, so even latest OpenVMS for x86-64 still contains some VAX assembly code, but it is compiled into LLVM IR and then the LLVM backend converts it to x86-64 ELF binaries.
No reason in principle why someone could not do the same thing with the 32-bit ARM assembly code in RISC OS. Likely would be easier than rewriting it all in a high-level language
HP did the same when migrating away from the PA RISC architecture.
IIRC as part of their testing they set it up so it would ingest, recompile and output code for the same architecture, and found that it could produce speed improvements due to context awareness.
Yes “MACRO-32” [0] is what I’m talking about and is still around - from Alpha it was ported to Itanium and now x86-64. Although to clarify, my understanding is it doesn’t take machine code as input, rather macro assembler source code - although I suppose you could use a disassembler to turn your VAX binary into assembler source and then try compiling it with MACRO-32.
VEST wasn’t actually a VM per se, it was a static binary translator - read in an OpenVMS VAX executable, write out an OpenVMS Alpha executable. VEST was only ever available for Alpha, but HP then created AEST which could do the same thing to translate Alpha executables to Itanium-and you could use VEST then AEST in sequence to port a VAX executable to Itanium.
However, VSI have said they have no plans to create an “IEST” to port Itanium executables to x86-64. I believe they face two big difficulties: (a) Itanium is a very complex and non-traditional architecture which makes binary translating it more of a challenge than it would be for a more mainstream architecture (b) legal risk due to aspects of it being covered by Intel patents (and unclear if Intel would license those patents on terms which would make an “IEST” commercially viable)
Tandem used something similar called The Accelerator to translate binaries from their proprietary CISC chips to MIPS, including parts of the NonStop operating system.
See Tandem Systems Review, Volume 8 Number 1 - Spring 1992
They came up with a rather ingenious solution - a compiler from VAX assembly to Alpha. And that was carried forward into the Itanium and now x86-64 ports, so even latest OpenVMS for x86-64 still contains some VAX assembly code, but it is compiled into LLVM IR and then the LLVM backend converts it to x86-64 ELF binaries.
No reason in principle why someone could not do the same thing with the 32-bit ARM assembly code in RISC OS. Likely would be easier than rewriting it all in a high-level language