The biggest reason I find aarch64 annoying to read and write are the sized register names.
`add w1, w2, w3` is the same as `add x1, x2, x3`, but with 32-bit instead of 64-bit values. By itself this isn't that bad, but it's misleading, because you can't mix them, e.g. `add x1, x2, w3` isn't valid, and it doesn't allow you to include the calling convention in the register names, like in RISC-V.
Now you have to remember which range of register numbers are function arguments, which are caller saved and callee saved.
In general, the instructions are very overloaded, which makes searching for and recognizing a specific type of instruction non-trivial.
Both of the above things get worse, once you enter NEON and floating point code. With RVV it isn't perfect either, because the type isn't encoded in every instruction, but rather as a global configurable vtype. However, the instructions them self are defined relative to the current vtype.
`add w1, w2, w3` is the same as `add x1, x2, x3`, but with 32-bit instead of 64-bit values. By itself this isn't that bad, but it's misleading, because you can't mix them, e.g. `add x1, x2, w3` isn't valid, and it doesn't allow you to include the calling convention in the register names, like in RISC-V. Now you have to remember which range of register numbers are function arguments, which are caller saved and callee saved.
In general, the instructions are very overloaded, which makes searching for and recognizing a specific type of instruction non-trivial.
Both of the above things get worse, once you enter NEON and floating point code. With RVV it isn't perfect either, because the type isn't encoded in every instruction, but rather as a global configurable vtype. However, the instructions them self are defined relative to the current vtype.