Dummy silicon, in the same way as the majority of Leonardo's Mona Lisa is dummy wood panel (which supports the painting applied on top of it and ensures its structural integrity)? But how is this different from other chips out there? Ok, I get it that this is because of the chiplet technology used, but in a "traditional" chip the dummy silicon that provides the structural integrity would just be part of the chip, while in this case it's separate?
>Excluding interconnects, the SRAM and CCD should add up to less than 20µm thick. To accommodate such small and fragile components, AMD has added a bulky layer of dummy silicon at the top and the bottom for structural integrity.
The article doesn't answer questions like whether this is unusual, if other CPUs historically have had a lot of dummy silicon, whether this is expensive or how it impacts the cost of production or how it affects the complexity of production itself. It's what I'd expect from modern journalism, but not really what I expect from good journalism.
The way nearly every CPU starting right from 4004 has worked is that they take a silicon wafer that's about half a mm thick, do a lot of photolithography, etching, deposition and other stuff to build the cpu on the top side of it, flip it upside down and bond it to the package. Only the very surface layer of the silicon is active in any way, the rest of the bulk is used for structural support and spreading heat laterally (necessary because heat is not evenly distributed at all, the hot spots get very hot). Power and signals come from the package below, heat is dissipated to the top.
The x3d chips change this, because in it there are two silicon dies bonded together, right on top of each other. The lower one of these dies gets through-silicon vias built into it, so it can provide power and signals for the top one. In prior generations, there was a normal CPU on the bottom, and they put the cache chip on top. For Zen5, they reversed that.
A complication is that apparently the process they use to bond them requires the top chip to be thinned. This means it's structurally weak and that heat spreads worse laterally, which would be bad for top clocks. So they bond another, thicker piece of silicon on top of it.
"requires the top chip to be thinned" and then "bond a thicker piece of silicon on top of it." That doesn't seem very efficient to me but I'm sure they know what they are doing.
Yeah. I think that other CPUs do also have a large chunk of 'dummy' silicon, except it's just the wafer that it's manufactured on the surface of, instead of a seperate part that's added after the wafer is ground down to allow for the connections through the back.
Yes. The article is click bait. With such a title I would have expected majority of the area to be dummy, but it is just structurally more silicon, exactly like a picture may be majority of its mass wood.
Your statement is incorrect. The analysis was made by a professional firm - dummy silicon shims are used because the dies are thinned, as per AMD's own disclosures. Those silicon shims are bonded to the compute and SRAM dies.
You aren't arguing with Tom's use of the term here - you are arguing with a semiconductor teardown specialist who pointed this out. They are extra chunks of silicon with no logic or transistors that are glued on. Hence, by every single definition of the term, they are dummy silicon.
I think the term "dummy silicon" is fair because those wafers don't have any transistors or wires on them but OTOH they also cost almost nothing so it's not as wasteful as it might sound.
Yes, they are bonded (glued-on) chunks of silicon with no logic. That is the definition of Dummy Silicon. The person who wrote the report is a professional chip analyst who does die deconstruction.
There's nothing bad about what AMD is doing here and the resulting product is amazing. I would like to see a similar teardown for Arrow Lake Foveros though.
