In general, the SRAM based units have a asic boot loader that may often be reconfigured with external pin logic. i.e. the chip configuration may be pulled from internal flash memory, sdcard, and external spi flash. Most designs I see place external spi flash chips next to the fpga, and the JTAG header in some convenient location.
While some modern high-performance fpga chips may have internal flash and an asic cpu... the configuration can generally still be updated with relative ease.
Notably, there are some exceptions where some chips may have fuses blown to lock it down, or were substituted with a One Time Programmable chip variant in production.
All that aside, the IP license to make it work will likely be unavailable for free, and high-speed/lvds layout is a black art requiring some pricey equipment to get clean performance.
One is often better off getting an overpriced xilinx PCIe development kit from a vendor, as most of the basic IP issues are solved... and one may focus on your core application.
Reverse engineering high-speed boards are way more work than most folks could imagine.
While some modern high-performance fpga chips may have internal flash and an asic cpu... the configuration can generally still be updated with relative ease.
Notably, there are some exceptions where some chips may have fuses blown to lock it down, or were substituted with a One Time Programmable chip variant in production.
All that aside, the IP license to make it work will likely be unavailable for free, and high-speed/lvds layout is a black art requiring some pricey equipment to get clean performance.
One is often better off getting an overpriced xilinx PCIe development kit from a vendor, as most of the basic IP issues are solved... and one may focus on your core application.
Reverse engineering high-speed boards are way more work than most folks could imagine.
Best regards, =3