It mapped very well to HW, but only to dumbest part of the hw.
at least from pov of someone dabbling in SDNs around 2014-2017 including deep guts implementation details of one commercial one...
OpenFlow encoded the approach of dumb ethernet switches, combined with Cisco Express Forwarding - which is a common aspect of many switching ASICs, but not entirety of them, even for Cisco.
It never abstracted that historic aspect, if anything the leaking was the internal model of OpenFlow (editing forwarding table) rather than internals HW (which sometimes was a systolic array of CPUs that exposed "tables" as detail of interaction but nothing actually fundamental).
All was fine so long, like CEF, you dumped everything to CPU/northbound API outside "IP with this address should go there, and TCP flow with those parameters go there", in case of early openflow bejbf essentially "packet with dstMAC shall go to port X".
This does not work well with acceleration engines, or in beefier chips the aforementioned systolic arrays or similar arrangements, outside of hardcoding idea of specific accelerators and their interface tables.
at least from pov of someone dabbling in SDNs around 2014-2017 including deep guts implementation details of one commercial one...
OpenFlow encoded the approach of dumb ethernet switches, combined with Cisco Express Forwarding - which is a common aspect of many switching ASICs, but not entirety of them, even for Cisco.
It never abstracted that historic aspect, if anything the leaking was the internal model of OpenFlow (editing forwarding table) rather than internals HW (which sometimes was a systolic array of CPUs that exposed "tables" as detail of interaction but nothing actually fundamental).
All was fine so long, like CEF, you dumped everything to CPU/northbound API outside "IP with this address should go there, and TCP flow with those parameters go there", in case of early openflow bejbf essentially "packet with dstMAC shall go to port X".
This does not work well with acceleration engines, or in beefier chips the aforementioned systolic arrays or similar arrangements, outside of hardcoding idea of specific accelerators and their interface tables.