Hacker Newsnew | past | comments | ask | show | jobs | submitlogin

Ssstrict is supposed to address the undefined behaviour problem, or at least it'll make undefined instructions actually trap.

https://github.com/riscv/riscv-profiles/blob/main/rva23-prof...



That's not really what I meant. It's very easy to configure which instructions or CSRs exist, and excluding custom extensions there are really only two options for behaviour, so you just have a flag `haveSomeExtension()` to enable the instructions and CSRs. The Sail model has some of these flags already.

If you write to a WARL field in a CSR the chip can use more or less any legalisation logic it wants. Configuring that is very difficult (though there is a decent attempt in riscv-config).


Yes I don't think Ssstrict is very complete. In fact while I was looking for it, I'm not sure it's been fully defined yet, beyond some postings on the tech-profiles list.




Guidelines | FAQ | Lists | API | Security | Legal | Apply to YC | Contact

Search: