Hm. The reason synchronization is needed is because the emulator must simulate the chip behaviours over time, and ensure that they act as if they are all behaving in real-time lock step. Might an alternative approach be to simply simulate each chip independently, in parallel, without synchronization, but "somehow" ensure that their behaviour is exactly corresponding to real time, so that time does not need to be "faked" by synchronization?
Yes, this is probably a recipe for disaster, and I have little idea what mechanism could be used to ensure time accuracy, but just a thought. (Perhaps an RTOS?) I also wonder what would be possible with FPGAs, whether programmable logic might provide a better approach to emulating these chips in synchrony.
Yes, this is probably a recipe for disaster, and I have little idea what mechanism could be used to ensure time accuracy, but just a thought. (Perhaps an RTOS?) I also wonder what would be possible with FPGAs, whether programmable logic might provide a better approach to emulating these chips in synchrony.