While that's a cool chip, it doesn't really apply here.
USB2.0 ports on the RPI4 only have 2.0 lines (from DWC2 inside the SOC).
USB3.0 ports on the RPI4 have both 2.0 and 3.0 lines going to it (both sets of lines for this port coming from the same place: the pcie connected usb controller).
Even though both of the above ports come with 2.0 lines, they're quite different in how they're implemented.
The chip you linked would be useful if that pcie controller didn't come with 2.0 connections.
Ah, cool. This is great info. I just assumed the 2.0 lines would have gone to the SoC still. I'll have to measure the CPU load again and make sure I'm plugged in to a blue port.
USB2.0 ports on the RPI4 only have 2.0 lines (from DWC2 inside the SOC). USB3.0 ports on the RPI4 have both 2.0 and 3.0 lines going to it (both sets of lines for this port coming from the same place: the pcie connected usb controller).
Even though both of the above ports come with 2.0 lines, they're quite different in how they're implemented.
The chip you linked would be useful if that pcie controller didn't come with 2.0 connections.