I think the desire to only use a single wire for signalling is understandable, at least in setups where there are physical wires, rather than tracks on a flex PCB, running from LED to LED.
Since every rising edge is the start of a new bit, encoding each bit with an H followed by an L makes the signal self-clocking. With this, the two sides don't need very accurate -- or shared -- clocks.
With the tolerances specified in the datasheet, to tell a zero from one the receiver only needs to tell whether a pulse is shorter (T0H) or longer (T1H) that 0.5us.
T0L and T1L are indistinguishable (their allowed durations overlap) and don't need to be measured by the receiver. That said, I do agree that it's weird that they weren't chosen such that T0H+T0L=T1H+T1L at the centre of the tolerance range.
That said, I do agree that it's weird that they weren't chosen such that T0H+T0L=T1H+T1L at the centre of the tolerance range.
It's likely they intended them to be the same, but for whatever reason the design characterisation discovered the distribution of periods are actually slightly different from the ideal design, so instead of trying to do a potentially very expensive redesign, they just documented the reality and left it at that.
I think the desire to only use a single wire for signalling is understandable, at least in setups where there are physical wires, rather than tracks on a flex PCB, running from LED to LED.
Since every rising edge is the start of a new bit, encoding each bit with an H followed by an L makes the signal self-clocking. With this, the two sides don't need very accurate -- or shared -- clocks.
With the tolerances specified in the datasheet, to tell a zero from one the receiver only needs to tell whether a pulse is shorter (T0H) or longer (T1H) that 0.5us.
T0L and T1L are indistinguishable (their allowed durations overlap) and don't need to be measured by the receiver. That said, I do agree that it's weird that they weren't chosen such that T0H+T0L=T1H+T1L at the centre of the tolerance range.