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Maybe EPIC [1] architectures need a revival. Rely on compilers to take advantage of explicit instruction-level parallelism, and keep the CPU dumb.

[1] https://en.wikipedia.org/wiki/Explicitly_parallel_instructio...



That failed for good reasons. Itanium processors ended up using out of order execution and speculation just like everyone else, because the compilers just don't have enough information compared to an out of order execution engine.


From Poulson onwards anyway. https://www.realworldtech.com/poulson/


Reminds me of the Mill ISA:

https://millcomputing.com/


> Rely on compilers to take advantage of explicit instruction-level parallelism, and keep the CPU dumb.

This very much is never going to be feasible for consumer and general purpose computing.


The ML folks are pulling themselves out of that rut now. There’s lots of interesting work going on for the next generation of compilers.




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