but any given core only has access to 16 soon to be 32mb

in Zen 1 and Zen 2, cores have direct or indirect access to the shared L3 cache in the same CCX. In the cross-CCX case the neighboring CCX cache can be accessed over the in-package interconnect without going through system DRAM.

this!

when i started with computers, they had a few KB of L2 cache, L3 did not exist. Main Memory was a few MB.