Don’t get me wrong, I think what those guys are doing is cool, but it’s 130nm, a fairly small die, and it’s not a fully custom ASIC. That’s how they’re getting the cost down to under $100K. “Degree of Customization: Only what is available through configuration of the design template”

Thanks for pointing that out. Yes, the $1mm number I cited in my post is the estimated raw cost of a full mask set for a relatively modern process in the 2Xnm or smaller range.

Definitely older processes have much cheaper mask sets -- in part because there are just fewer metal layers, and fewer & cheaper masks required to image the transistors when the wavelength of light used (193nm) is close to the line width of the devices themselves.