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FPGA Softcore SoC Shootout (justanotherelectronicsblog.com)
97 points by zdw on July 8, 2020 | hide | past | favorite | 6 comments



If you are interested in a framework for stitching together a soft SoC there is a great framework call FuseSOC. It supports several of the cores used here. : https://fusesoc.net/

There is also the LiteX project: https://github.com/enjoy-digital/litex


I'm slightly surprised the author didn't mention the core I work on Ibex: https://github.com/lowRISC/ibex but maybe not too surprised as it's primary target isn't FPGA softcore, though it does work fine for this purpose.

It's got an extensive verification environment (though relies on UVM so you need closed tools to run it, we have a verilator setup for running RISC-V compliance and arbitrary binaries), good documentation and we're pushing the performance up (you can get 3.09 CoreMark/MHz with the current master and that will increase with some branch prediction work I'm currently doing). It's configurable so you can choose your own trade offs between size and performance. Plus we've got support for the B (bitmanip) extension, which our verification environment also tests.

All cores have their pros and cons and Ibex is no exception but if you're looking for an open CPU core I think it's well worth a look.


Any idea what clockrate ibex would achieve on his hardware? Being able to hit 125 MHz is useful e.g. for gig-e support.

Bitmanip extension is pretty awesome.


Excellent analysis! Do you have CoreMark scores instead of DMIPS?


Neither is really that great. Embench should be getting there maybe.


I've seen their repo, it's pretty lame. CoreMark is still difficult for compilers to optimize away so I think it's better than DMIPS.




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