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> Our current estimates remain at 48 nm poly pitch and 30 nm metal pitch. Those dimensions yield an estimated device density of 171.3 MTr/mm².

I just sized up 1mm between my fingers.

Um. WOW. Really. Wow.



For reference a 64-bit Pentium 4 core was (drum roll) 125Million transistors. And it was 100x bigger (112mm^2)


Wow at that too.

To be honest, one of the things I was considering when posting the GP was the sheer impossibility of leveling anything more precise than hand-wavy, drunk opinions about the end-to-end security state of that much, well, entropy.

It's gotten almost like a bizarre version of inverted quicksand, where instead of it being bad because you're sinking into sand, it's bad because the sand is shrinking into nothingness from between your fingers.

The next few years are going to be VERY interesting, I think.

IIUC, OOo and branch prediction have kind of been the CPU engineering meal ticket workaround to "solving" the memory latency problem (IIUC), and now everyone apparently has to rethink that.

My favorite would be the "disappearance" of the A20 line though. As in, it's there, it's doing it's thing, but everyone collectively forgot it existed, and now everybody needs a microcode update and an SGX cert respin AGAIN.

And all this without access to specialized tooling (the kind that evolves over a decade, regardless of knowledge), AND the fact that we're (apparently?) only forgetting about (seemingly?) little things at this point. Haha...ha...




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