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gameswithgo on Nov 6, 2018 | parent | context | favorite | on: AMD Announces 7nm Rome CPUs and MI60 GPUs

how often can 64 cores be effectively utilized without bumping up on memory throughput as a limiter?

This is pretty challenging at 32 cores! I know these chips ship with big l3 cache but l3 cache isn't so fast either.

imtringued on Nov 7, 2018 [–]

I'm wondering if we will ever reach a point at which even interpreted languages will be bottlenecked on memory bandwidth rather than cache misses.

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