Come on, it's a middle of 2016, everyone gotta know about projects like http://icoboard.org/ , https://olimex.wordpress.com/2016/05/06/ice40hx1k-evb-open-s... , etc. projects. They allow to have completely open-source process to bring up RISC-V CPUs on a reverse-engineered FPGA. When they collect enough funds (if people of the world will give it to them), they will make ASIC silicon too. The only risk is that big corporations won't give up their prerogative of being the only parties who make the world better, subsume RISC-V and shove out closed-down RISC-V chips like they did before. But how it should work is that there should be competition between classical NDA-ridden and close-down stuff and open RISC-V, to let customers decide what they want in a particular case.

Ah, I thought you were talking about ASICs. Are those FPGAs big enough to support RISC-V?

The closed corporate versions of RISC-V thing is very likely and probably will become the easiest way to get a RISC-V chip.

> Are those FPGAs big enough to support RISC-V

RISC-V is a flexible and configurable architecture, with support ranging from small MCUs to 128-bit ISA which nobody else have yet (for a general-purpose ISA) to tagged memory (which failed to rule the world in 1970ies but now might be just used when gives benefit).

Those FPGAs of course run an MCU variant of RISC-V (as we started with talking about Arduino), e.g. https://github.com/cliffordwolf/picorv32