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Given the lack of CCR in the RISC-V I doubt that he would be very impressed by it's ease of use..


I'm not convinced that's a big deal. You just end up using a register of your choice and sticking a flag in it.


OK, please show me the code to do a long addition or a long multiplication in RISC-V. (long as in 'multiple words')


Here. 64-bit addition on RV32I.

    ; input 1 (msb r1, lsb r2)
    ; input 2 (r3, r4)
    ; output (r5, r6)
    xori    r5, r4, -1
    sltu    r5, r5, r2
    add     r6, r4, r2
    add     r5, r5, r3
    add     r5, r5, r1
This is what I mean. Outside a few applications (mostly asymmetric crypto) nobody cares that it takes five instructions instead of two. Remember that this is the same processor that outright omits multiplication from the core spec.




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